Problem sets

The complete problem catalog. The % chip is your predicted chance of solving each problem right now.

Getting Started

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Getting Started64%Output Zero64%

Verilog Language / Basics

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Simple wire64%Four wires64%Inverter64%AND gate64%NOR gate64%XNOR gate64%Declaring wires36%7458 chip36%

Verilog Language / Vectors

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Vectors64%Vectors in more detail64%Vector part select36%Bitwise operators36%Four-input gates64%Vector concatenation operator36%Vector reversal 136%Replication operator36%More replication15%

Verilog Language / Modules: Hierarchy

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Modules🔒64%Connecting ports by position🔒64%Connecting ports by name🔒64%Three modules🔒36%Modules and vectors🔒36%Adder 1🔒36%Adder 2🔒15%Carry-select adder🔒15%Adder-subtractor🔒36%

Verilog Language / Procedures

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Always blocks (combinational)🔒64%Always blocks (clocked)🔒64%If statement🔒64%If statement latches🔒36%Case statement🔒64%Priority encoder🔒36%Priority encoder with casez🔒36%Avoiding latches🔒36%

Verilog Language / More Verilog Features

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Conditional ternary operator🔒36%Reduction operators🔒64%Gates and vectors 100🔒64%Vector reversal 2🔒36%Population count🔒36%100-bit ripple-carry adder🔒15%100-digit BCD adder🔒5%

Circuits / Combinational Logic / Basic Gates

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Exams/m2014 q4h🔒64%Exams/m2014 q4i🔒64%Exams/m2014 q4e🔒64%Exams/m2014 q4f🔒64%Exams/m2014 q4g🔒64%Gates🔒64%7420 chip🔒64%Truth tables🔒36%Two-bit equality🔒64%Circuit A🔒64%Circuit B🔒64%Combine circuits A and B🔒36%Ring or vibrate?🔒64%Thermostat🔒64%3-bit population count🔒36%Gates and vectors🔒36%Even longer vectors🔒36%

Circuits / Combinational Logic / Multiplexers

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2-to-1 multiplexer🔒64%2-to-1 bus multiplexer🔒64%9-to-1 multiplexer🔒36%256-to-1 multiplexer🔒36%256-to-1 4-bit multiplexer🔒15%

Circuits / Combinational Logic / Arithmetic Circuits

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Half adder🔒64%Full adder🔒64%3-bit ripple-carry adder🔒36%4-bit adder🔒36%Signed addition overflow🔒15%100-bit adder🔒36%4-digit BCD adder🔒15%

Circuits / Combinational Logic / Karnaugh Map to Circuit

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3-variable K-map🔒36%4-variable K-map🔒15%K-map with don't-cares🔒15%K-map: checkerboard🔒15%Minimum SOP and POS🔒15%K-map to circuit (one group)🔒36%K-map to circuit (wrap-around groups)🔒15%K-map implemented with a multiplexer🔒15%

Circuits / Sequential Logic / Latches and Flip-Flops

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D flip-flop🔒64%D flip-flops🔒64%DFF with reset🔒36%DFF with reset value🔒36%DFF with asynchronous reset🔒36%DFF with byte enable🔒15%D latch🔒36%Async-reset D flip-flop🔒36%Sync-reset D flip-flop🔒36%DFF with XOR feedback🔒36%Mux and DFF🔒36%Shift register stage🔒36%Three flip-flops and gates🔒15%JK flip-flop🔒36%Detect an edge🔒36%Detect both edges🔒36%Edge capture register🔒15%Dual-edge triggered flip-flop🔒15%

Circuits / Sequential Logic / Counters

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Four-bit binary counter🔒36%Decade counter🔒36%Decade counter again🔒36%Slow decade counter🔒36%Counter 1-12🔒15%Counter 1000🔒5%4-digit decimal counter🔒15%12-hour clock🔒5%

Circuits / Sequential Logic / Shift Registers

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4-bit shift register🔒36%Left/right rotator🔒15%Left/right arithmetic shift by 1 or 8🔒15%5-bit LFSR🔒15%3-bit LFSRexternal🔒15%32-bit LFSR🔒15%Shift register (m2014_q4k)🔒36%Shift register (2014_q4b)external🔒15%Circuit from a shift register (3-input LUT)🔒15%

Circuits / Sequential Logic / More Circuits

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Rule 90🔒15%Rule 110🔒5%Conway's Game of Life 16x16🔒2%

Circuits / Sequential Logic / Finite State Machines

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Simple FSM 1 (asynchronous reset)🔒36%Simple FSM 1 (synchronous reset)🔒36%Simple FSM 2 (asynchronous reset)🔒15%Simple FSM 2 (synchronous reset)🔒15%FSM 3: combinational logic only🔒15%FSM 3: one-hot logic by inspection🔒15%FSM 3 (asynchronous reset)🔒15%FSM 3 (synchronous reset)🔒15%Water reservoir controller🔒15%Lemmings 1: walking🔒15%Lemmings 2: falling🔒15%Lemmings 3: digging🔒15%Lemmings 4: splat🔒5%One-hot FSM: derive logic by inspection🔒15%PS/2 packet parser🔒15%PS/2 packet parser and datapath🔒15%Serial receiver🔒15%Serial receiver and datapath🔒15%Serial receiver with parity checking🔒5%HDLC frame synchronization🔒5%Mealy FSM: recognize 101🔒15%Serial two's complementer (Moore)🔒15%Serial two's complementer (Mealy)🔒15%FSM: count 1s in 3-cycle windows🔒5%FSM from a state-assigned table🔒15%FSM logic: next-state bit Y0 and z🔒15%FSM next-state logic: bit Y1🔒15%One-hot FSM logic: Y2 and Y4🔒15%Six-state FSM (m2014 q6)🔒15%Six-state FSM (2012 q2)🔒15%One-hot FSM logic (2012 q2)🔒15%FSM: priority arbiter🔒5%FSM from a spec: f and g🔒5%

Circuits / Building Larger Circuits

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Counter with period 1000🔒15%4-bit shift register and down counter🔒15%FSM: sequence 1101 recognizer🔒15%FSM: enable shift register for 4 cycles🔒15%FSM: the complete timer controller🔒5%The complete timer🔒2%FSM: one-hot logic equations🔒5%

Verification: Reading Simulations / Finding bugs in code

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Mux🔒36%NAND🔒36%Mux4🔒36%Add/sub🔒36%Case statement🔒36%

Verification: Reading Simulations / Circuits from simulation waveforms

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Combinational circuit 1🔒36%Combinational circuit 2🔒36%Combinational circuit 3🔒36%Combinational circuit 4🔒36%Combinational circuit 5🔒15%Combinational circuit 6🔒36%Sequential circuit 7🔒15%Sequential circuit 8🔒5%Sequential circuit 9🔒15%Sequential circuit 10🔒5%

Verification: Writing Testbenches

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Clockexternal🔒36%Testbench 1external🔒36%AND gate testbenchexternal🔒36%Testbench 2external🔒36%T flip-flop testbenchexternal🔒36%

CS450

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Timer🔒36%Two-bit saturating counter🔒36%History shift register🔒15%Gshare predictor🔒2%