Six-state FSM (2012 q2)

Implement the FSM described by the following state diagram (shown here as a table), with input w and Moore output z:

Present state	Next state if w=0	Next state if w=1	Output z
A	A	B	0
B	D	C	0
C	D	E	0
D	A	F	0
E	D	E	1
F	D	C	1

reset is synchronous, active-high, and forces the machine to state A. Use separate combinational always blocks for the next-state and output logic if you like, or a single clocked block plus an assign — any correct style is accepted.