Serial receiver

A serial line (like classic RS-232) idles at logic 1. Each byte is framed as: one start bit (0), then 8 data bits, then one stop bit (1) — one bit per clock cycle. Frames may be back-to-back: a start bit can immediately follow a stop bit.

Build an FSM that watches the in bitstream and identifies correctly framed bytes:

• While idle (line history correct, waiting), a 0 on in is a start bit: the next 8 cycles carry the data bits, and the cycle after that must carry the stop bit.
• If the stop-bit cycle has in = 1, the frame is valid: assert done for exactly one cycle, the cycle after the stop bit. During that done cycle, in may already be the start bit of the next frame.
• If the stop-bit cycle has in = 0 (framing error), do not assert done; instead wait until in = 1 (the eventual stop bit), and only then resume waiting for a start bit. A 0 seen while waiting out a framing error is not a start bit.

The active-high reset is synchronous and puts the FSM in the idle/waiting state.