Modules and vectors

This is the previous shift register widened to 8 bits, plus an output selector.

You are given an 8-bit D flip-flop module:

module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

On every rising edge of clk, q captures d (all 8 bits at once).

1. Chain three my_dff8 instances into an 8-bit, 3-stage shift register clocked by clk, with top_module's d feeding the first stage.
2. Add a 4-to-1 multiplexer that picks how much delay appears at the output q, controlled by sel[1:0]:

sel	q
0	d itself (no delay)
1	output of the 1st flip-flop (1 cycle of delay)
2	output of the 2nd flip-flop (2 cycles)
3	output of the 3rd flip-flop (3 cycles)

The mux is not provided — build it yourself (a chained ternary, or an always @(*) block with a case, both work).