Serial two's complementer (Mealy)

Implement the same serial two's complementer as the previous problem, but this time as a Mealy machine with only two states. The input x delivers a number one bit per cycle, LSB first; the output z is the two's complement of the stream, produced in the same cycle as the corresponding input bit (combinational output).

The bit-serial negation rule: copy every bit up to and including the first 1; invert every bit after it. That gives:

State	Meaning	z	next state
A	no 1 seen yet	z = x	x=1 → B, x=0 → A
B	a 1 has been seen	z = ~x	B (stay forever)

The machine has an asynchronous, active-low reset resetn that returns it to state A.