← ProblemsCircuits / Sequential Logic / Shift Registers
3-bit LFSR
15%shift-registersflip-flopsImplement the 3-bit LFSR from the midterm schematic, targeting a DE1-SoC-style board interface:
KEY[0]is the clockKEY[1]isL, a synchronous parallel-load controlSW[2:0]is the parallel load valueLEDR[2:0]shows the register contents
On each rising edge of KEY[0]: when L is 1, the register loads SW; otherwise it steps the LFSR:
r[0] <= r[2]
r[1] <= r[0]
r[2] <= r[1] ^ r[2]
Note: because the clock here is one bit of a bus (KEY[0]), this problem is graded externally — solve it in an external simulator, then mark it complete.
This problem can't be auto-graded here yet — it needs a full behavioral Verilog simulator. Solve it in an external simulator, then record your result so your learning path stays accurate.