Counter 1-12

Design a counter that counts 1 through 12 inclusive, built around the provided 4-bit counter count4 (included below your module — do not modify it). count4 loads d when load is 1, otherwise counts up when enable is 1:

count4(clk, enable, load, d[3:0] -> Q[3:0])

Your top module has a synchronous active-high reset (resets the count to 1, with priority over enable) and an enable input. Besides the count Q[3:0], you must also output the exact control signals you feed to the internal count4 instance, so the grader can check your control logic:

• c_enable = enable
• c_load = reset OR (Q == 12 AND enable) — reload at the wrap or on reset
• c_d = 4'd1 when c_load is 1, and 4'd0 otherwise