Serial receiver and datapath

Extend the serial receiver with a datapath that outputs the received byte. The framing FSM is unchanged:

• Idle line is 1. A frame is: start bit (0), 8 data bits, stop bit (1); one bit per cycle; frames may be back-to-back.
• done is asserted for one cycle, the cycle after a correct stop bit. On a framing error (stop-bit cycle has in = 0), wait until in = 1 before resuming the search for a start bit.
• Active-high synchronous reset returns to idle.

New output out_byte[7:0]: when done is high it must hold the received data byte. The serial line sends the least-significant bit first, so the first data bit lands in out_byte[0] and the last in out_byte[7].

To keep the behavior fully specified, implement out_byte as an 8-bit right-shift register that updates only at the end of each of the 8 data-bit cycles: shift right one position and load in into bit 7 (out_byte <= {in, out_byte[7:1]}). At all other times out_byte holds its value; reset does not clear it. After 8 shifts the byte sits in out_byte LSB-first, exactly when done goes high.