Gshare predictor

2%cpu-archcountersshift-registers

Build a gshare branch predictor with a 7-bit program counter, a 7-bit global history register, and a pattern history table (PHT) of 128 two-bit saturating counters (same encoding as the two-bit counter problem: 2'b00 strongly not-taken … 2'b11 strongly taken). Gshare XORs the PC with the global history to index the PHT, letting one table entry distinguish different histories of the same branch.

Prediction (combinational outputs, plus a history update):

  • Index: predict_pc ^ predict_history (the current history register).
  • predict_taken = the MSB (bit 1) of the indexed PHT entry.
  • predict_history outputs the current global history register.
  • When predict_valid = 1, on the next rising clock edge the history register shifts the prediction in: {predict_history[5:0], predict_taken}.

Training (on each rising clock edge):

  • When train_valid = 1, update the PHT entry at index train_pc ^ train_history: if train_taken = 1 increment it (saturating at 3), else decrement it (saturating at 0).
  • When train_valid = 1 and train_mispredicted = 1, also recover the global history register to the state just after the mispredicted branch completes: {train_history[5:0], train_taken}. Recovery takes priority over the prediction shift when both happen in the same cycle.

Same-cycle interaction: training and prediction may occur in the same cycle. If training writes the same PHT entry that the prediction is reading, the prediction uses the old (pre-training) value — PHT writes take effect only at the clock edge.

areset is an asynchronous active-high reset that clears the history register to 0 and sets every PHT entry to 2'b01 (weakly not-taken).