Shift register stage

Implement one stage of a shift register with load and enable controls. The flip-flop triggers on the rising edge of clk, and the controls have priority order:

• If L is 1, load: Q captures R.
• Else if E is 1, shift: Q captures w (the bit arriving from the neighboring stage).
• Otherwise (L = 0 and E = 0), hold: Q keeps its current value.

So: Q <= L ? R : (E ? w : Q).