T flip-flop testbench

You are given a T flip-flop with synchronous, active-high reset:

module tff ( input clk, input reset, input t, output q );

Write a testbench that resets the flip-flop, then leaves it toggling:

1. Generate a free-running clock (e.g. 10 ps period, starting at 0).
2. At time 0, assert reset = 1 with t = 0, and hold both for one full clock cycle so at least one rising edge samples the reset.
3. Then deassert reset = 0 and set t = 1 for the rest of the simulation, so q toggles on every subsequent rising clock edge.

Note: This problem requires a behavioral testbench, which isn't graded in-browser — write and run it in an external Verilog simulator, then mark your result here.