FSM from a spec: f and g

Design an FSM with inputs x and y and outputs f and g, controlled by a synchronous, active-low reset resetn. The required behaviour, in order:

1. While resetn = 0 (at clock edges), the machine sits in an initial state with f = 0 and g = 0.
2. In the first clock cycle after resetn is released (i.e., the cycle following the first rising edge at which resetn = 1), assert f = 1 for exactly one cycle. f is 0 at all other times.
3. Starting in the cycle after the f pulse, monitor x: the machine searches for the pattern x = 1, 0, 1 in three successive cycles. While searching, track the longest useful prefix: a 1 always counts as a (possibly new) first bit; after 1, 0, a 0 means the search restarts from nothing.
4. In the cycle immediately after the pattern 1, 0, 1 completes, set g = 1.
5. With g now 1, examine y for at most two clock cycles (the first two cycles in which g = 1). If y = 1 in either of those cycles, keep g = 1 permanently (until reset). If y was 0 in both, set g = 0 permanently (until reset).

Equivalently, as a transition table (outputs are Moore-style: f = 1 only in FPULSE, g = 1 only in G1, G2, and GON):

State	Meaning	Next state
IDLE	held by reset	FPULSE
FPULSE	f = 1 this cycle	SEEK0
SEEK0	no prefix of 101 yet	x ? SEEK1 : SEEK0
SEEK1	seen 1	x ? SEEK1 : SEEK10
SEEK10	seen 1,0	x ? G1 : SEEK0
G1	first g = 1 cycle	y ? GON : G2
G2	second g = 1 cycle	y ? GON : GOFF
GON	g = 1 forever	GON
GOFF	g = 0 forever	GOFF