FSM: enable shift register for 4 cycles

Once the start command is seen, the controller must open the shift register for exactly four clock cycles to capture the delay value. This exercise isolates that timing behavior, using reset itself as the trigger.

Build an FSM with a synchronous reset whose only output is shift_ena:

• On any clock edge where reset = 1, the FSM (re-)enters the first of four "shift" states. shift_ena is 1 in all four of these states.
• On each edge where reset = 0, the FSM advances one state: through the remaining three shift states, then into a final idle state where shift_ena = 0. It stays idle forever — until the next reset.

Consequences to get right:

• For a single-cycle reset pulse, shift_ena is high for exactly 4 cycles, starting with the cycle that follows the edge that sampled reset = 1.
• If reset is held for several cycles, the FSM sits in the first shift state the whole time (shift_ena stays 1), then takes the remaining 3 cycles after release.
• Registers power up to 0; encode your states so the FSM powers up in the first shift state (shift_ena = 1), just as if reset had been applied.