Testbench 2

You are given this design under test:

module q7 ( input clk, input in, input [2:0] s, output out );

Write a testbench that instantiates q7 and generates these input waveforms:

• clk: starts at 0 and inverts every 5 ps (10 ps period), forever.
• s and in follow this schedule, holding between events:

time (ps)	s	in
0	2	0
10	6	0
20	2	1
30	7	0
40	0	1
70	0	0

(s stays 0 from 40 ps onward; in drops back to 0 at 70 ps and stays there.)

Use one initial/always pair for the clock and a separate initial block for s and in.

Note: This problem requires a behavioral testbench, which isn't graded in-browser — write and run it in an external Verilog simulator, then mark your result here.