← ProblemsVerilog Language / Procedures
If statement latches
36%proceduresconditionalsA common bug: in combinational logic, if some path through your if statements doesn't assign the output, the synthesizer must remember the old value — it infers a latch, which is almost never what you wanted.
The starter code below contains two such bugs. The intended behavior is:
shut_off_computershould be 1 only whencpu_overheatedis 1, and 0 otherwise.keep_drivingshould be 1 only while you have not arrived and the gas tank is not empty; in every other situation it should be 0.
The buggy code only says what happens in one branch and stays silent in the other, so both outputs latch. Fix it by making sure each output is assigned a value on every path through its always block (add else branches).