FSM: sequence 1101 recognizer

The timer is armed by a serial command: the bit pattern 1101 arriving on data, one bit per clock cycle. Build the part of the controller that watches for it.

Implement a Moore FSM with a synchronous reset. The FSM monitors data at every clock edge. As soon as the four most recently received bits are 1101, assert start_shifting = 1 and lock: stay in that state with the output high, ignoring data, until the next reset returns the FSM to searching.

Timing: start_shifting first becomes 1 in the cycle after the clock edge that samples the final 1 of the pattern (a Moore output of the "found" state).

Track partial matches correctly:

• In the stream 1 1 1 0 1 the extra leading 1 is harmless — the last four bits are 1101, so this is a detection.
• After 1 1 0 0 the partial match is dead and the search starts over from nothing.

Registers power up to 0; encode your states so that the power-up state is the initial "nothing seen yet" search state.