Shift register (2014_q4b)

Build the 4-bit shift register from the exam schematic out of four identical stages. Each stage is a flip-flop with a load/shift mux in front of it:

Q <= L ? R : (E ? w : Q)

(L = parallel load from R, E = shift enable taking the serial input w, otherwise hold.)

Wire four instances into a shift register and connect them to the board interface:

• KEY[0] — clock; KEY[1] — E; KEY[2] — L; KEY[3] — w (serial input)
• SW[3:0] — the parallel-load values R
• LEDR[3:0] — the register outputs; w shifts in at the LEDR[3] end and moves toward LEDR[0]

Write the stage as a separate module and instantiate it four times.

Note: because the clock here is one bit of a bus (KEY[0]), this problem is graded externally — solve it in an external simulator, then mark it complete.