FSM logic: next-state bit Y0 and z

For the FSM of the previous problem, suppose the state flip-flops are external to your block: you receive the current state y[2:0] as an input and must produce, combinationally, the next-state bit Y0 (bit 0 of the next state) and the output z. The same state-assigned table applies:

Present state y[2:0]	Next state if x=0	Next state if x=1	Output z
000	000	001	0
001	001	100	0
010	010	001	0
011	001	010	1
100	011	100	1

Y0 is therefore 1 exactly when the next-state code in the table is odd. A clk port is present (the surrounding circuit's flip-flops use it) but your logic is purely combinational and should not use it. Only the five listed state codes are ever applied to y.