DFF with byte enable

Create a 16-bit register (16 D flip-flops) with byte-wise write enables and an active-low synchronous reset resetn.

At every rising edge of clk:

• If resetn is 0, the whole register is cleared to 0 (reset wins over the enables).
• Otherwise, byteena[1] controls the upper byte: when it is 1, q[15:8] captures d[15:8]; when 0, the upper byte holds its value.
• Likewise byteena[0] controls the lower byte q[7:0] ← d[7:0].

Each byte can be written independently of the other.