Mealy FSM: recognize 101
15%fsmfsm-designDesign a Mealy-type finite state machine that watches a serial input x (one bit per clock cycle) and recognizes the sequence 1-0-1. Output z must be asserted in the same clock cycle in which the final 1 of the sequence arrives — that is, z is a combinational function of the current state and x, not a registered output.
Overlapping sequences must be recognized: in the input stream 1 0 1 0 1, the pattern occurs twice (cycles 3 and 5), and z must pulse both times — the trailing 1 of a match also serves as the leading 1 of the next potential match.
The machine has an asynchronous, active-low reset aresetn that forces it back to the "nothing seen yet" state. Three states are sufficient:
| State | Meaning | x=0 → | x=1 → | z |
|---|---|---|---|---|
| A | no useful prefix seen | A | B | 0 |
| B | last bit was the leading 1 | C | B | 0 |
| C | have seen 1,0 | A | B | 1 when x=1, else 0 |
(Note B's self-loop on x=1: a fresh 1 is always a valid new prefix. From C on x=1 the match completes and the machine returns to B, ready for an overlapping match.)