← ProblemsVerilog Language / Modules: Hierarchy
Modules
64%hierarchyHardware designs are built from modules that contain other modules. Instantiating a module places a copy of that hardware inside yours and lets you wire up its ports.
You are given a module mod_a (already written for you, below your code — leave it untouched). Its port list, in order, is one output followed by two inputs:
module mod_a ( output out, input in1, input in2 );
In this self-contained version, mod_a computes the AND of its two inputs — but you don't need to know that to solve the problem.
Inside top_module, create one instance of mod_a and connect its output to out and its two inputs to a and b. You may connect ports by position or by name.