FSM: one-hot logic equations
5%fsmfsm-designGiven a version of the timer controller FSM with a one-hot state encoding, derive (some of) its next-state and output equations by inspection. This is a purely combinational exercise: the current 10-bit state vector is an input.
The FSM (same as the timer controller):
| State | Transitions | Meaning |
|---|---|---|
S | d=1 → S1, d=0 → S | search: nothing seen |
S1 | d=1 → S11, d=0 → S | seen 1 |
S11 | d=1 → S11, d=0 → S110 | seen 11 |
S110 | d=1 → B0, d=0 → S | seen 110 |
B0 | → B1 (always) | shift cycle 1 |
B1 | → B2 (always) | shift cycle 2 |
B2 | → B3 (always) | shift cycle 3 |
B3 | → Count (always) | shift cycle 4 |
Count | done_counting=1 → Wait, else Count | counting |
Wait | ack=1 → S, else Wait | done, awaiting ack |
Outputs: shift_ena in B0–B3; counting in Count; done in Wait.
One-hot encoding — state bit i corresponds to: S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9.
Write the equations for B3_next, S_next, S1_next, Count_next, Wait_next (the next-state bits for those five states) and for done, counting, shift_ena.
Derivation rule (important): each next-state bit is the OR, over every arrow into that state, of (source state bit AND arrow condition); each output is the OR of the state bits where it is asserted. Use exactly these equations — the grader drives arbitrary state vectors, including non-one-hot ones, so any "simplification" that relies on the one-hot assumption in another way will mismatch.