FSM: the complete timer controller

Now combine the two previous FSMs into the timer's complete control FSM. The datapath (shift register, counters) is not part of this exercise — done_counting and ack arrive as plain inputs, and the FSM produces only control outputs. All outputs are Moore (functions of the current state). reset is synchronous and returns the FSM to the search state.

The control sequence:

1. Search — watch data for the serial pattern 1101 (same partial-match rules as the recognizer exercise). All outputs are 0.
2. Shift — starting the cycle after the edge that samples the pattern's final 1, assert shift_ena for exactly 4 cycles (the datapath would capture the delay value during these cycles). data is ignored by the FSM during this phase.
3. Count — deassert shift_ena, assert counting. Stay here until a clock edge where done_counting = 1.
4. Done — deassert counting, assert done. Stay here until a clock edge where ack = 1, then return to Search and start over.

At most one of shift_ena, counting, done is 1 at any time. done_counting and ack have no effect outside their respective phases, and data has no effect outside the search phase.

Registers power up to 0; encode your states so the FSM powers up in the initial search state.