Three modules

You are given a D flip-flop module:

module my_dff ( input clk, input d, output q );

On every rising edge of clk, q takes the value of d.

Instantiate three of them and chain them head-to-tail to build a 3-stage, 1-bit shift register: top_module's input d feeds the first flip-flop, each flip-flop's q feeds the next one's d, and the last flip-flop's q drives the output q. All three share the same clk.

You will need to declare internal wires to carry the signals between stages.