Dual-edge triggered flip-flop

Build a circuit that behaves like a dual-edge triggered D flip-flop: q captures d on both the rising and falling edges of clk.

The catch: FPGAs don't have dual-edge flip-flops, and writing always @(posedge clk or negedge clk) is not synthesizable (it isn't a valid flip-flop sensitivity list). You must emulate the behavior using ordinary single-edge flip-flops — for example, one flip-flop clocked on each edge plus a multiplexer (or an XOR trick) to produce the output.