← ProblemsVerilog Language / Modules: Hierarchy
Adder-subtractor
36%hierarchyarithmeticAn adder becomes an adder–subtractor using the two's-complement identity a - b = a + ~b + 1: invert b and add 1 via the carry-in.
Build a 32-bit adder–subtractor from two of the provided add16 modules ({cout, sum} = a + b + cin) plus a little glue logic:
- XOR the 32-bit
bwithsubreplicated 32 times ({32{sub}}). Whensub = 0this leavesbunchanged; whensub = 1it inverts every bit. - Feed the XOR result, in two 16-bit halves, into the same two-add16 ripple structure as before.
- Connect
subto the carry-in of the lower adder — that supplies the "+1".
So the circuit computes a + b when sub = 0 and a - b when sub = 1.