← ProblemsCircuits / Sequential Logic / Finite State Machines
FSM: priority arbiter
5%fsmfsm-designDesign an arbiter FSM that hands out grants g[3:1] in response to requests r[3:1] from three devices. Device 1 has the highest priority, device 3 the lowest.
- In the idle state A, no grant is asserted (
g = 3'b000). At each clock edge while in A: ifr[1] = 1, move to state B; else ifr[2] = 1, move to state C; else ifr[3] = 1, move to state D; otherwise stay in A. - In state B, assert
g[1] = 1(only). Remain in B as long asr[1]stays 1; whenr[1] = 0at a clock edge, return to A. - In state C, assert
g[2] = 1(only). Remain whiler[2] = 1; return to A whenr[2] = 0. - In state D, assert
g[3] = 1(only). Remain whiler[3] = 1; return to A whenr[3] = 0.
A grant, once given, is not preempted by a higher-priority request — the device keeps its grant until it drops its own request.
resetn is an asynchronous, active-low reset that forces the machine to state A.