← ProblemsCircuits / Sequential Logic / Finite State Machines

Six-state FSM (m2014 q6)

15%fsm

Implement the complete six-state FSM from the previous two problems, with input w and output z:

Present stateNext state if w=0Next state if w=1Output z
ABA0
BCD0
CED0
DFA0
EED1
FCD1

z is a Moore output: it is 1 whenever the machine is in state E or F. reset is synchronous, active-high, and forces the machine to state A. You may choose any state encoding you like.