← ProblemsVerilog Language / Modules: Hierarchy

Adder 1

36%hierarchyarithmetic

You are given a 16-bit adder module with carry-in and carry-out:

module add16 ( input [15:0] a, input [15:0] b, input cin,
               output [15:0] sum, output cout );

It computes {cout, sum} = a + b + cin.

Instantiate two of them to build a 32-bit adder: one add16 adds the lower 16 bits of a and b, the other adds the upper 16 bits. The lower adder's carry-in is 0; its carry-out feeds the upper adder's carry-in. The final carry-out is ignored — sum is just 32 bits.

Use part-selects like a[15:0] and a[31:16] to slice the operands, and assemble the two 16-bit sums into the 32-bit result.