← ProblemsVerification: Writing Testbenches
AND gate testbench
36%testbenchYou are given an AND gate to verify:
module andgate ( input [1:0] in, output out );
Write a testbench that instantiates the gate and drives its 2-bit input through all four combinations, in increasing order, holding each value for 10 ps:
| time (ps) | in |
|---|---|
| 0 | 2'b00 |
| 10 | 2'b01 |
| 20 | 2'b10 |
| 30 | 2'b11 |
Connect the gate's output to a wire so the simulator can observe it.
Note: This problem requires a behavioral testbench, which isn't graded in-browser — write and run it in an external Verilog simulator, then mark your result here.
This problem can't be auto-graded here yet — it needs a full behavioral Verilog simulator. Solve it in an external simulator, then record your result so your learning path stays accurate.