Reduction operators

Parity checking is a simple way to detect single-bit errors when transmitting data. Build a circuit that computes the even parity bit for an 8-bit byte: parity is the XOR of all 8 input bits, so that the 9 bits together always contain an even number of 1s.

Writing in[0] ^ in[1] ^ ... ^ in[7] works, but Verilog's reduction operators apply one operator across every bit of a vector, producing a 1-bit result — perfect here.