256-to-1 4-bit multiplexer

Build a 4-bit wide, 256-to-1 multiplexer. The 256 four-bit words are packed into one 1024-bit input vector:

• sel = 0 selects in[3:0], sel = 1 selects in[7:4], sel = 2 selects in[11:8], and so on up to sel = 255 selecting in[1023:1020].

The catch: a classic part-select like in[sel*4+3 : sel*4] is illegal because both bounds are variable. Verilog-2001's indexed part select exists precisely for this — a variable starting position with a constant width.