← ProblemsVerification: Writing Testbenches
Clock
36%testbenchYou are given a design under test with this declaration:
module dut ( input clk );
Write a testbench — a module with no ports — that instantiates one copy of dut and drives its clk input with a clock signal of 10 ps period: start the clock at 0, then invert it every 5 ps, forever (5 ps low, 5 ps high).
The timescale is 1 ps, so a delay of #5 is 5 ps.
Note: This problem requires a behavioral testbench, which isn't graded in-browser — write and run it in an external Verilog simulator, then mark your result here.
This problem can't be auto-graded here yet — it needs a full behavioral Verilog simulator. Solve it in an external simulator, then record your result so your learning path stays accurate.