← ProblemsVerilog Language / More Verilog Features
Gates and vectors 100
64%vectorsbasicsBuild a combinational circuit with a 100-bit input in[99:0] and three outputs:
out_and— the AND of all 100 input bitsout_or— the OR of all 100 input bitsout_xor— the XOR of all 100 input bits
With 100 inputs, writing the expression out bit by bit is hopeless — the reduction operators do each of these in one short assign.