The complete timer

Assemble the complete timer from the pieces you have built: the controller FSM, the 4-bit shift/down-count register, and the modulo-1000 counter.

Operation. reset is synchronous and returns the controller to its search state. Then, repeatedly:

1. Search data for the serial pattern 1101 (one bit per clock edge, same partial-match rules as before).
2. Shift in the delay — the 4 bits immediately following the pattern, MSB-first: the first of those four bits becomes delay[3], the last becomes delay[0]. This takes the 4 cycles starting the cycle after the edge that samples the pattern's final 1.
3. Count — assert counting for exactly (delay + 1) × 1000 clock cycles (so delay = 0 counts 1000 cycles and delay = 15 counts 16000 cycles).
4. Done — deassert counting, assert done, and hold until a clock edge where ack = 1; then return to searching. done is 0 at all other times.

The count output is the remaining time, and to make grading deterministic its behavior is fully specified. count is the 4-bit shift/down-count register itself, updated at every clock edge by exactly one rule (the current phase decides; a simultaneous reset does not change which rule applies on that edge — it only changes the phase for later cycles):

• During each of the 4 shift cycles: shift left, data entering at bit 0 (so it holds the delay once shifting completes).
• While counting is asserted: decrement by 1 exactly on the clock edge that completes each block of 1000 counting cycles — except the edge completing the final block (when count is already 0) leaves it at 0. Thus count reads delay for the first 1000 counting cycles, delay − 1 for the next 1000, …, and 0 for the final 1000.
• At all other times — searching, done, and whenever reset is asserted — it holds its value. reset never clears this register; it powers up at 0.

So between a completed count and the next shift-in, count stays at 0; after a reset that interrupts shifting or counting, it simply holds whatever it contained.