4-bit shift register and down counter

The timer's delay register does double duty: it is loaded serially with a 4-bit value, then later counts that value down. Build this 4-bit register:

• When shift_ena = 1, shift the register left by one position each clock cycle, with data entering at bit 0. Shifting a value in over four cycles is therefore MSB-first: the first bit shifted in ends up in q[3].
• When count_ena = 1 (and shift_ena = 0), decrement the register by 1 each cycle. Decrementing past 0 wraps to 15 — ordinary 4-bit arithmetic.
• If both enables are 1 on the same cycle, shifting takes precedence. (The full timer never asserts both at once, but your circuit must behave this way so it grades deterministically.)
• When neither enable is 1, hold the current value.

There is no reset; the register simply powers up at 0.