4-bit shift register

Build a 4-bit right-shift register with asynchronous reset, parallel load, and enable:

• areset — asynchronous, active-high reset that clears the register to 0
• load — load data[3:0] into the register (has priority over ena)
• ena — shift right: q[3] becomes 0, q[0] (the LSB) is shifted out and lost

If both load and ena are 1, only the load happens.