Counter 1000

From a 1000 Hz clock, derive a signal OneHertz that pulses high for one clock cycle every 1000 cycles — usable as the enable for a one-second timer.

Build the divider as a 3-digit BCD counter (000 to 999) using three instances of the provided bcdcount module (included below your module — do not modify it). bcdcount has a synchronous reset to 0 and counts 0–9 when enabled:

bcdcount(clk, reset, enable -> Q[3:0])

You must also output the three enable signals you feed to the counters, with digit 0 the ones digit:

• c_enable[0] = 1 (the ones digit always counts)
• c_enable[1] = 1 when digit 0 equals 9
• c_enable[2] = 1 when digit 0 and digit 1 both equal 9
• OneHertz = 1 when all three digits equal 9 (i.e., the count is 999)