Mux and DFF

Implement one stage of a loadable shift register: a 2-to-1 multiplexer feeding a D flip-flop.

At every rising edge of clk, the flip-flop captures the mux output:

• If L (load) is 1, the mux selects r_in.
• If L is 0, the mux selects q_in.

So: Q <= L ? r_in : q_in.