Edge capture register

For each bit of a 32-bit input vector, capture when the signal changes from 1 in one clock cycle to 0 the next (a 1→0 transition).

"Capture" means the output bit is set the cycle after the transition and then stays 1 (sticky) until the register is cleared by the active-high synchronous reset.

Each output bit behaves like an SR flip-flop: it is set one cycle after a 1→0 transition on its input bit, and reset at a rising clock edge when reset is 1. If both would happen in the same cycle, reset takes precedence.