← ProblemsVerilog Language / Modules: Hierarchy
Connecting ports by name
64%hierarchyConnecting by position breaks silently if a module's port order ever changes. The safer style is to connect ports by name.
You are given the same six-port mod_a, but this time its ports are not in a convenient order. Its port names are:
out1, out2, a, b, c, d
(As before, out1 is the AND of the four inputs and out2 is their OR.)
Instantiate mod_a and connect each mod_a port to the top-level signal of the same name (mod_a's a to top-level a, out1 to out1, and so on), using the .port_name(signal) syntax for every connection.